While conventional resolution-enhancement technologies (RET), such as optical proximity correction (OPC), are widely applied in advanced design-to-manufacturing processes in order to improve manufacturability and yield of integrated circuit layouts, such resolution enhancements are difficult to verify and the verification results do not necessarily translate to systematic methods of correcting RET/OPC. Furthermore, conventional RET/OPC cannot be applied incrementally or reconfigured selectively, due to proximity and hierarchical interactions of the enhancements. This resulted in “one shot” RET/OPC operations to an entire circuit layout, followed by a verification step, wherein a negative verification result necessitated adjustment to the RET/OPC settings and a reapplication of the full set of adjusted RET/OPC operations to the entire circuit layout. This approach is inefficient and time-consuming. The conventional approach presents a further disadvantage in that it prohibits the application of RET/OPC to standard cells and intellectual property (IP) cores in a way that allows such layouts to be reused as well as characterized early in the design flow.
Accordingly, a fundamentally new approach to RET/OPC is needed, allowing incremental, selective and locally reconfigurable applications of RET/OPC early in the design flow.